1. Field of the Invention
The present invention is related to a lower power consumption designing method of a semiconductor integrated circuit.
2. Description of the Related Art
In connection with increases of circuit scales in semiconductor integrated circuits, increases of electric power consumed in these semiconductor integrated circuits may cause a problem. Therefore, low power consumption designing methods have been conventionally developed and carried out in order to reduce the power consumption. More specifically, since portable appliances have been recently popularized, it is a very important aspect that power consumption of semiconductor integrated circuits mounted on these portable appliances may be reduced as much as possible.
As low power consumption designing methods for semiconductor integrated circuits, such a conventional low power consumption designing method requires a repetition of layout designing operation, and therefore, may induce an increase in developing cost. In the conventional designing method, after a layout designing operation has been accomplished, magnitudes of currents flowing through respective circuit portions within the semiconductor integrated circuit are confirmed, and then, the layout is corrected in order to reduce power consumption.
In contrast to the above-described designing method, another conventional designing method has been conventionally carried out in which power consumption is estimated before a layout designing operation, and the estimated power consumption is reflected to the layout designing operation. Concretely speaking, a designing method disclosed in JP-A-9-246389 is carried out in order to reduce power consumption as follows: That is, a logic simulation of a semiconductor integrated circuit is carried out which should be designed; power consumption is estimated by totalizing toggle operation times of each of circuit portions; and a restriction condition in a layout designing operation is determined based upon the estimated power consumption.
Also, a designing method disclosed in JP-A-2002-318826 is performed as follows: That is, while an attention is paid to such a fact that power consumption as to two sorts of flip-flops having different operating characteristics is changed, depending upon data operating rates and input waveform transition times, such flip-flops are individually selected, the power consumption of which becomes low in response to a data operating rate and an input waveform transition time every logic path.
FIG. 9 is a flow chart for describing a conventional low power consumption designing method of a semiconductor integrated circuit. In FIG. 9, a semiconductor integrated circuit designing method is constituted by a logic synthesizing step 201, an arrangement synthesizing step 204, a clock tree synthesis step 207, and a wiring line optimizing step 208. In the respective stages of this conventional low power consumption designing method, the above-described electric power optimizing method is employed, and in order to perform this electric power optimizing method, uniform toggle information is applied to the respective circuit portions.
However, in the above-explained conventional low power consumption designing method, both the structural elements and the wiring line systems have been determined after the logic synthesizing operation, and thereafter, the logic simulation is carried out. As a consequence, there is such a problem that lengthy time is necessarily required until the toggle information is acquired.
Also, in order to shorten the time, such a designing method for applying the uniform toggle information has been employed. However, with respect to such uniform toggle information, an information amount is small and precision is low. As a result, there is another problem that such a low power consumption capable of achieving a maximum effect cannot be realized.